1. Field of the Invention
This invention relates generally to non-volatile semiconductor memory devices and, more particularly, to electrically erasable programmable read only memory (EEPROM) devices of the NAND type.
2. Description of Related Art
In nonvolatile semiconductor memories, memory cells of a metal oxide semiconductor (MOS) transistor structure with stacked floating and control gates are generally used. In NAND type EEPROMs, a plurality of such memory cells are connected in series to make up a NAND cell unit. One end of the NAND cell unit is connected through a select gate transistor to a bit line; the other end is coupled via a select gate transistor to a source line.
With miniaturization of memory cells, the distance between neighboring memory cells within a NAND cell unit is becoming shorter. Due to this, the floating gate of a memory cell is becoming considerably larger not only in capacitive coupling with respect to the memory cell's channel region and control gate but also in capacitive coupling to the floating and control gates of its neighboring memory cell.
In the case of NAND-EEPROMs, data write and erase are performed by applying a voltage between a control gate and a channel (p-type well region) to thereby inject electrons from the channel onto the floating gate in the form of a tunnel current or, alternatively, draw electrons out of the floating gate toward the channel. Principally in this case, a potential of the floating gate is determinable by a capacitive coupling ratio, which is defined by a capacitance between the control and floating gates and a capacitance between the floating gate and the channel.
However, when the distance between memory cells is shortened, the capacitance between neighboring memory cells affects the above-noted coupling ratio. The series-connected memory cells within a NAND cell unit are the same in structure as one another, and a variation factor of the coupling ratio among them is a form parameter. When looking at a memory cell which is located adjacent to a select gate transistor, its one side is a memory cell, and the other side thereof is the select gate transistor. The select gate transistor is different from the memory cell both in structure and in operating voltage. For this reason, those memory cells next to select gate transistors are different in write/erase characteristics from the remaining memory cells.
A detailed explanation will be given of a data erase event with reference to FIG. 13 below. In FIG. 13, there is shown a bias relationship during data erasing with respect to a range within a NAND cell unit, which includes a select gate transistor on the bitline BL side and its subsequent two memory cells. Data erase is such that “all-at-a-time” erase is performed in units of blocks. In this case, apply a voltage of zero volts (0V) to all word lines WL while applying an erase voltage Vera of 18V (Vera=18V) to a p-type well region. Set a select gate SG and a bit line BL in an electrically floating state. Although not shown in FIG. 13, a source line and a select gate line on the source line side also are similarly set in the floating state.
Whereby, at a memory cell, electrons on its floating gate FG are released or drawn out into the channel thereof. At this time, in a memory cell of a word line WL0 adjacent to a select gate line SGD, the potential of its floating gate FG is affected by a capacitance C3 between the floating gate FG and the select gate SG. More specifically, when setting the select gate SG in the floating state, its potential becomes almost equal to the erase voltage Vera of the p-type well. The result of this is that the floating gate FG of the memory cell of word line WL0 becomes higher in potential than floating gates of the other memory cells due to the presence of the coupling via the capacitance C3 between itself and control gate SG. This potential increase causes the memory cell of interest to be difficult to be erased. The same goes with a memory cell that is selected by a word line in close proximity to a select gate line on the source line side.
FIG. 14 graphically shows threshold voltages after data erase (Erase Vth) of a test structure with respect to each of sixteen word lines WL, wherein the test structure has a NAND cell unit made up of sixteen memory cells. The erase threshold voltages of the memory cells associated with word lines WL0 and WL15 next to the select gates are higher by about 0.8V than those of the other memory cells (i.e. the cells connected to word lines WL1-WL14).
A similar problem occurs in data write events. Data write is performed by setting the p-type well at 0V, precharging the channels of a NAND cell unit in a way pursuant to the data to be written, and thereafter applying a write voltage Vpgm to a selected word line. Whereby, in a memory cell which is given logic “0” data and whose channel is set at Vss, electrons are injected onto the floating gate thereof. In a memory cell that is given logic “1” data with its channel being precharged to Vcc and thus set in the floating state (namely, write inhibit memory cell), its channel potentially rises up due to the capacitive coupling so that any electron injection hardly occurs. This write technique is called the “self-boosting” scheme. Non-selected word lines are applied an intermediate voltage to ensure that hold data are not destroyed.
FIG. 15 shows word-line dependency characteristics of after-write threshold voltages (Program Vth) in the case of performing a write operation while sequentially applying write pulses to all of sixteen word lines within a NAND cell unit. Regarding the word lines WL0 and WL15 that are located next to the select gate lines, these are different in operation conditions during write from the other wordlines, due to the capacitive coupling from the select gate lines. For this reason, writing is slower than writing of the other memory cells, with the threshold voltage lowered by about 0.5V.
Additionally, an improved version of the self-boost scheme is available, which is aimed at efficient voltage boost control of only certain memory cells along a selected word line by applying the word lines neighboring upon the selected word line a voltage lower than that of the other non-selected word lines. This scheme is known as “local self-boost” scheme (for example, see U.S. Pat. No. 6,011,287). The USP '287 also shows, in its FIG. 13, another example which sets the select gate line not in the floating state but at 0V at the time of data erasing.
It has been proposed to employ a technique for setting the threshold voltages of select gate transistors in a way conformity with operation conditions during data writing by taking account of the fact that the voltage to be applied to select gate lines affects the writing characteristics (for example, refer to Published Japanese Patent Application No. 11-86571). This handles as a problem a voltage to be transferred by a select gate transistor from a bit line toward a NAND cell channel.
As apparent from the foregoing, prior art NAND-EEPROMs are faced with a problem which follows: as the device miniaturization makes progress, the capacitive coupling of from a select gate transistor to its neighboring memory cell becomes innegligible, resulting in an increase in value variation of erase threshold voltage and write threshold voltage of the memory cells within a NAND cell unit.